1. Field of the Invention
The present invention relates to a master slave flip-flop circuit in which consumed electric power is reduced.
2. Description of Related Art
FIG. 7 is a constitutional view of a conventional master slave flip-flop circuit. In FIG. 7, 21 indicates a clock input driver for receiving a clock signal CLK, outputting a positive phase clock signal T having the same phase as that of the clock signal CLK and outputting an inverted phase clock signal TC having a phase opposite to that of the clock signal CLK. 22 indicates a master latch circuit set to a data though state in response to the low level of the clock signal CLK and set to a data holding state in response to the high level of the clock signal CLK to load a new value of a data signal D in each data though state and to hold the new value in the data holding state set just after the data though state. 23 indicates a slave latch circuit set to a data though state in response to the high level of the clock signal CLK and set to a data holding state in response to the low level of the clock signal CLK to load the new value held in the master latch circuit 22 of the data holding state in each data though state and to hold the new value as a preceding value in the data holding state set just after the data through state. 24 indicates an output driver for inverting and outputting the preceding value held in the slave latch circuit 23.
The clock input driver 21 has both a first inverter and a second inverter. The first inverter is composed of a p-channel metal oxide semiconductor (PMOS) transistor 21a and an n-channel metal oxide semiconductor (NMOS) transistor 21b connected to each other at a drain connection terminal. The second inverter is composed of PMOS transistor 21c and an NMOS transistor 21d connected to each other at a drain connection terminal. The inverted phase clock signal TC is output from the drain connection terminal of the first inverter, and the positive phase clock signal T is output from the drain connection terminal of the second inverter.
The master latch circuit 22 has a switching element 22a, a switching element 22b, a third inverter composed of a PMOS transistor 22c and an NMOS transistor 22d and a fourth inverter composed of a PMOS transistor 22e and an NMOS transistor 22f. The switching element 22a and the third and fourth inverters are serially connected to each other in that order, and the switching element 22b is connected in parallel to the third and fourth inverters. A data signal D is input to the switching element 22a, and the value of the data signal D held in the master latch circuit 22 is output from a drain connection terminal of the fourth inverter.
The slave latch circuit 23 has a switching element 23a, a switching element 23b, a fifth inverter composed of a PMOS transistor 23c and an NMOS transistor 23d and a sixth inverter composed of a PMOS transistor 23e and an NMOS transistor 23f. The switching element 23a and the fifth and sixth inverters are serially connected to each other in that order, and the switching element 23b is connected in parallel to the fifth and sixth inverters. The value held in the master latch circuit 22 is input to the switching element 23a, an inverted output signal QC having a phase opposite to that of the data signal D is output from a drain connection terminal of the fifth inverter, and a positive output signal Q having the same phase as that of the data signal D is output from a drain connection terminal of the sixth inverter.
The output driver 24 has both a seventh inverter composed of a PMOS transistor 24a and an NMOS transistor 24b and an eighth inverter composed of a PMOS transistor 24c and an NMOS transistor 24d. The seventh and eighth inverters are connected in parallel to each other. The inverted output signal QC of the slave latch circuit 23 is input to the seventh inverter, and a positive phase output data signal Qout having the same phase as that of the data signal D is output from a drain connection terminal of the seventh inverter. Also, the positive output signal Q of the slave latch circuit 23 is input to the eighth inverter, and an inverted phase output data signal QCout having a phase opposite to that of the data signal D is output from a drain connection terminal of the eighth inverter.
Each of the switching elements 22a, 22b, 23a and 23b is composed of a PMOS transistor and an NMOS transistor, and an on state and an off state are alternately set in the switching element in response to the level changes of both the positive phase clock signal T and the inverted phase clock signal TC. The timing of the on and off states in the switching element 22a is the same as that in the switching element 23b, and the timing of the on and off states in the switching element 22b is the same as that in the switching element 23a. The on and off states of each switching element are set in correspondence to the high and low levels of the clock signal CLK.
For example, when the clock signal CLK set to the high level is changed to the low level, the positive phase clock signal T is set to the low level, and the inverted phase clock signal TC is set to the high level. Each of the switching elements 22a and 23b is set to the on state according to the clock signals T and TC, and each of the switching elements 22b and 23a is set to the off state according to the clock signals T and TC. In this case, the master latch circuit 22 is set to the data through state, and the data signal D passes through the switching element 22a and is input to the third and fourth inverters composed of the PMOS transistors 22c and 22e and the NMOS transistors 22d and 22f. Therefore, a new value of the data signal D is loaded in the master latch circuit 22. At this time, in the slave latch circuit 23, the switching circuit 23a is set to the off state, and the switching circuit 23b is set to the on state. Therefore, the slave latch circuit 23 is set to the data holding state so as to hold a preceding value which is received in the data through state just before the data holding state. The preceding value is output to the output driver 24 as the positive output signal Q, and an inverted value of the preceding value is output to the output driver 24 as the inverted output signal QC.
In contrast, when the clock signal CLK is set to the high level, the positive phase clock signal T is set to the high level, and the inverted phase clock signal TC is set to the low level. Each of the switching elements 22a and 23b is set to the off state according to the clock signals T and TC, and each of the switching elements 22b and 23a is set to the on state according to the clock signals T and TC. In this case, the master latch circuit 22 is set to the data holding state so as to hold the new value which is received in the data through state set just before the data holding state, and the slave latch circuit 23 is set to the data through state to receive the new value held in the master latch circuit 22.
Therefore, the data through state and the data holding state are alternately set in the master latch circuit 22 in response to the clock signal CLK, the data holding state and the data through state different from the state of the master latch circuit 22 are alternately set in the slave latch circuit 23 in response to the clock signal CLK, and the positive phase output data signal Qout and the inverted phase data signal Qcout are output from the output driver 24.
However, because the conventional master slave flip-flop circuit has the above-described configuration, twelve transistors composed of the PMOS transistor 21a, the NMOS transistor 21b, the PMOS transistor 21c, the NMOS transistor 21d, the four PMOS transistors of the switching elements 22a, 22b, 23a and 23b and the four NMOS transistors of the switching elements 22a, 22b, 23a and 23b are operated in response to the clock signal CLK. In this case, both a charging current and a discharging current depending on parasitic capacitance (or gate capacitance) based on the gate electrode of each transistor flows through the gate electrode of the transistor each time the transistor is turned on or off in response to the clock signal, and electric power is consumed in the twelve transistors. Therefore, a problem has arisen that it is difficult to reduce electric power consumed in a semiconductor integrated circuit including the conventional master slave flip-flop circuit.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional master slave flip-flop circuit, a master slave flip-flop circuit in which consumed electric power is reduced.
The object is achieved by the provision of a master slave flip-flop circuit including a master latch circuit, a slave latch circuit and circuit state setting control means. The disconnection of a first line from a line set to a first electric potential and the connection of a second line to a line set to a second electric potential is performed by the circuit state setting control means in response to a first level of a clock signal to set the master latch circuit to a data through state and to set the slave latch circuit to a data holding state. The connection of the first line to the line set to the first electric potential and the disconnection of the second line from the line set to the second electric potential is performed by the circuit state setting control means in response to a second level of the clock signal to set the master latch circuit to the data holding state and to set the slave latch circuit to the data through state. In the master latch circuit, input data is received in the data through state and is held as master output data in the data holding state. In the slave latch circuit, the master output data is received in the data through state and is held as slave output data in the data holding state. The slave output data is output from the slave latch circuit.
Accordingly, because only the circuit state setting control means is operated in response to the clock signal to merely perform the connection and disconnection of the first and second lines, the number of transistors operated in synchronization with the clock signal can be considerably reduced, an amount of both a charging current and a discharging current depending on parasitic capacitance based on gate electrodes of the transistors can be considerably reduced, and the electric power consumed in the master slave flip-flop circuit can be considerably reduced.